dcn321_resource.c
Source contains low-bit mask syntaxMegabyte-scale size constant in source
SHA-256834bddc523c790d680177f0aceaec1764e1b0591a582f7b614b4f2040bdfbf4f
MaleculeH₂(Db₂Mg)
Evidence
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * th …
19:67… RWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn32/dcn32_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn32/dcn32_resource.h"
35#include "dcn321_resource.h"
36
37#include "dcn20/dcn20_resource.h"
38#include "dcn30/dcn30_resource.h"
39
40#include "dml/dcn321/dcn321_fpu.h"
41
42#include "dcn10/dcn10_ipp.h"
43#include "dcn30/dcn30_hubbub.h"
44#include "dcn31/dcn31_hubbub.h"
45#include "dcn32/dcn32_hubbub.h"
46#include "dcn32/dcn32_mpc.h"
47#include "dcn32/dcn32_hubp.h"
48#include "irq/dcn32/irq_service_dcn32.h"
49#include "dcn32/dcn32_dpp.h"
50#include "dcn32/dcn32_optc.h"
51#include "dcn20/dcn20_hwseq.h"
52#include "dcn30/dcn30_hwseq.h"
53#include "dce110/dce110_hwseq.h"
54#include "dcn30/dcn30_opp.h"
55#include "dcn20/dcn20_dsc.h"
56#include "dcn30/dcn30_vpg.h"
57#include "dcn30/dcn30_afmt.h"
58#include "dcn30/dcn30_dio_stream_encoder.h"
59#include "dcn32/dcn32_dio_stream_encoder.h"
60#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61#include "dcn31/dcn31_hpo_dp_link_encoder.h"
62#include "dcn32/dcn32_hpo_dp_link_encoder.h"
63#include "dcn31/dcn31_apg.h"
64#include "dcn31/dcn31_dio_link_encoder.h"
65#include "dcn32/dcn32_dio_link_encoder.h"
66#include "dcn321/dcn321_dio_link_encoder.h"
1676:16… < pool->base.res_cap->num_timing_generator; i++)
1677 if (pipe_fuses & 1 << i)
1678 num_pipes--;
1679
⋯4 lines
1711:42… _size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1712
1713 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1714 dc->caps.cache_line_size = 64;
1715 dc->c …
2043:33… ze = DCN3_2_DET_SEG_SIZE;
2044
2045 /* init DC limited DML2 options */
2046 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2047 dc->dml2_dc_power_options.use_clock …