Benign rust 221,744 installs Download

jxl_simd 0.7.1

“High performance Rust implementation of a JPEG XL decoder - SIMD support code”

Caret or XOR expression textRust asm! inline assembly macro
SHA-2561091a80abd3e82473bc2ae2c6941ea8bcc0350463f99ab3c4109e2302b217135

Evidence

imports crate::impl_i16_array_interface neon.rs · lines 1–21
1// Copyright (c) the JPEG XL Project Authors. All rights reserved.
2//
3// Use of this source code is governed by a BSD-style
4// license that can be found in the LICENSE file.
5
6use std::arch::aarch64::*;
7use std::ops::{
8 Add, AddAssign, BitAnd, BitAndAssign, BitOr, BitOrAssign, BitXor, BitXorAssign, Div, DivAssign,
9 Mul, MulAssign, Neg, Sub, SubAssign,
10};
11
12use super::super::{
13 F32SimdVec, I16SimdVec, I32SimdVec, SimdDescriptor, SimdMask, SimdMask16, U8SimdVec, U16SimdVec,
14};
15use crate::{U32SimdVec, U64SimdVec, impl_i16_array_interface};
16
17// Safety invariant: this type is only ever constructed if neon is available.
18#[derive(Clone, Copy, Debug)]
19pub struct NeonDescriptor(());
20
21impl NeonDescriptor {
Rust asm! inline assembly macro neon.rs · lines 450–455
450:36… aligned stores.
451 unsafe {
452 std::arch::asm!(
453 "fcvtn {out:v}.4h, {inp:v}.4s",
454 inp = in(vreg) this.0,
455 out = out(vr …
Caret or XOR expression text neon.rs · lines 796–805
796:34… cNeon {
797 type Output = I32VecNeon;
798 fn_neon! {
799 fn bitxor(this: I32VecNeon, rhs: I32VecNeon) -> I32VecNeon {
800 I32VecNeon(veorq_s32(this.0, rhs.0), this.1)
801 }
⋯4 lines
Rust synchronous or async test attribute scalar.rs · lines 634–642
634:39… {
635 (
636 $name:ident
637 ) => {
638 paste::paste! {
639 #[test]
640 fn [<$name _scalar>]() {
641 use $crate::SimdDescriptor;
642 $name($crate::ScalarDescriptor …
imports arbtest::arbitrary::Unstructured lib.rs · lines 670–691
670:17… .store(mem);
671 }
672 };
673}
674
675pub(crate) use impl_i16_array_interface;
676
677#[cfg(test)]
678mod test {
679 use arbtest::arbitrary::Unstructured;
680
681 use crate::{
682 F32SimdVec, I16SimdVec, I32SimdVec, ScalarDescriptor, SimdDescriptor, SimdMask16,
683 U8SimdVec, U16SimdVec, U64SimdVec, test_all_instruction_sets,
684 };
685
⋯6 lines

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